#ifndef __MACH_LA_LS2K500_H
#define __MACH_LA_LS2K500_H

#include <asm/loongarch.h>

/* CHIP CONFIG regs */
#define LS_GENERAL_CFG0				PHYS_TO_UNCACHED(0x1fe10100)
#define LS_GENERAL_CFG1				PHYS_TO_UNCACHED(0x1fe10104)
#define LS_GENERAL_CFG2				PHYS_TO_UNCACHED(0x1fe10108)
#define LS_GENERAL_CFG3				PHYS_TO_UNCACHED(0x1fe1010c)
#define LS_GENERAL_CFG4				PHYS_TO_UNCACHED(0x1fe10110)
#define LS_GENERAL_CFG5				PHYS_TO_UNCACHED(0x1fe10114)
#define LS_SAMPLE_CFG0				PHYS_TO_UNCACHED(0x1fe10120)
#define LS_CHIP_HPT_LO				PHYS_TO_UNCACHED(0x1fe10130)
#define LS_CHIP_HPT_HI				PHYS_TO_UNCACHED(0x1fe10134)

#define LS_NODE_PLL_L				PHYS_TO_UNCACHED(0x1fe10400)
#define LS_NODE_PLL_H				PHYS_TO_UNCACHED(0x1fe10404)
#define LS_DDR_PLL_L				PHYS_TO_UNCACHED(0x1fe10408)
#define LS_DDR_PLL_H				PHYS_TO_UNCACHED(0x1fe1040c)
#define LS_SOC_PLL_L				PHYS_TO_UNCACHED(0x1fe10410)
#define LS_SOC_PLL_H				PHYS_TO_UNCACHED(0x1fe10414)
#define LS_PIX0_PLL_L				PHYS_TO_UNCACHED(0x1fe10418)
#define LS_PIX0_PLL_H				PHYS_TO_UNCACHED(0x1fe1041c)
#define LS_PIX1_PLL_L				PHYS_TO_UNCACHED(0x1fe10420)
#define LS_PIX1_PLL_H				PHYS_TO_UNCACHED(0x1fe10424)
#define LS_FREQ_SCALE				PHYS_TO_UNCACHED(0x1fe10428)

#define NODE_L1DIV_OUT_SHIFT		24
#define NODE_L1DIV_LOOPC_SHIFT		16
#define NODE_L1DIV_REF_SHIFT		8
#define NODE_L1DIV_OUT_WIDTH		6
#define NODE_L1DIV_LOOPC_WIDTH		8
#define NODE_L1DIV_REF_WIDTH		6
#define NODE_L1DIV_OUT_MARK		    0x3f
#define NODE_L1DIV_LOOPC_MARK		0xff
#define NODE_L1DIV_REF_MARK		    0x3f

#define DDR_L2DIV_OUT_HDA_SHIFT		8
#define DDR_L2DIV_OUT_NET_SHIFT		0
#define DDR_L1DIV_OUT_SHIFT		    24
#define DDR_L1DIV_LOOPC_SHIFT		16
#define DDR_L1DIV_REF_SHIFT		    8
#define DDR_L2DIV_OUT_HDA_WIDTH		6
#define DDR_L2DIV_OUT_NET_WIDTH		6
#define DDR_L1DIV_OUT_WIDTH		    6
#define DDR_L1DIV_LOOPC_WIDTH		8
#define DDR_L1DIV_REF_WIDTH		    6
#define DDR_L2DIV_OUT_HDA_MARK		0x3f
#define DDR_L2DIV_OUT_NET_MARK		0x3f
#define DDR_L1DIV_OUT_MARK		    0x3f
#define DDR_L1DIV_LOOPC_MARK		0xff
#define DDR_L1DIV_REF_MARK		    0x3f

#define SOC_L2DIV_OUT_GMAC_SHIFT	8
#define SOC_L2DIV_OUT_SB_SHIFT		0
#define SOC_L1DIV_OUT_SHIFT		    24
#define SOC_L1DIV_LOOPC_SHIFT		16
#define SOC_L1DIV_REF_SHIFT		    8
#define SOC_L2DIV_OUT_GMAC_WIDTH	6
#define SOC_L2DIV_OUT_SB_WIDTH		6
#define SOC_L1DIV_OUT_WIDTH		    6
#define SOC_L1DIV_LOOPC_WIDTH		8
#define SOC_L1DIV_REF_WIDTH		    6
#define SOC_L2DIV_OUT_GMAC_MARK		0x3f
#define SOC_L2DIV_OUT_SB_MARK		0x3f
#define SOC_L1DIV_OUT_MARK		    0x3f
#define SOC_L1DIV_LOOPC_MARK		0xff
#define SOC_L1DIV_REF_MARK			0x3f

#define PIX_L1DIV_OUT_SHIFT			24
#define PIX_L1DIV_LOOPC_SHIFT       16
#define PIX_L1DIV_REF_SHIFT			8
#define PIX_L1DIV_OUT_WIDTH			6
#define PIX_L1DIV_LOOPC_WIDTH	    8
#define PIX_L1DIV_REF_WIDTH			6
#define PIX_L1DIV_OUT_MARK			0x3f
#define PIX_L1DIV_LOOPC_MARK	    0xff
#define PIX_L1DIV_REF_MARK			0x3f

#define FREQSCALE_LSU_SHIFT			27
#define FREQSCALE_PRINT_SHIFT	    24
#define FREQSCALE_APB_SHIFT			20
#define FREQSCALE_USB_SHIFT			16
#define FREQSCALE_SATA_SHIFT	    12
#define FREQSCALE_SB_SHIFT			8
#define FREQSCALE_GPU_SHIFT			4
#define FREQSCALE_NODE_SHIFT	    0
#define FREQSCALE_LSU_MARK			0x7
#define FREQSCALE_PRINT_MARK	    0x7
#define FREQSCALE_APB_MARK			0x7
#define FREQSCALE_USB_MARK			0x7
#define FREQSCALE_SATA_MARK			0x7
#define FREQSCALE_SB_MARK			0x7
#define FREQSCALE_GPU_MARK			0x7
#define FREQSCALE_NODE_MARK			0x7


#define LS_GPIO_SKIP_64_OFFSET			(0x20)
#define LS_GPIO_00_31_DIR				PHYS_TO_UNCACHED(0x1fe10430)
#define LS_GPIO_32_63_DIR				PHYS_TO_UNCACHED(0x1fe10434)
#define LS_GPIO_00_31_IN				PHYS_TO_UNCACHED(0x1fe10438)
#define LS_GPIO_32_63_IN				PHYS_TO_UNCACHED(0x1fe1043c)
#define LS_GPIO_00_31_OUT				PHYS_TO_UNCACHED(0x1fe10440)
#define LS_GPIO_32_63_OUT				PHYS_TO_UNCACHED(0x1fe10444)

#define LS_GPIO_0_7_MULTI_CFG			PHYS_TO_UNCACHED(0x1fe10490)
#define LS_GPIO_8_15_MULTI_CFG			PHYS_TO_UNCACHED(0x1fe10494)
#define LS_GPIO_16_23_MULTI_CFG			PHYS_TO_UNCACHED(0x1fe10498)
#define LS_GPIO_24_31_MULTI_CFG			PHYS_TO_UNCACHED(0x1fe1049c)
#define LS_GPIO_32_39_MULTI_CFG			PHYS_TO_UNCACHED(0x1fe104a0)
#define LS_GPIO_40_47_MULTI_CFG			PHYS_TO_UNCACHED(0x1fe104a4)
#define LS_GPIO_48_55_MULTI_CFG			PHYS_TO_UNCACHED(0x1fe104a8)
#define LS_GPIO_56_63_MULTI_CFG			PHYS_TO_UNCACHED(0x1fe104ac)
#define LS_GPIO_64_71_MULTI_CFG			PHYS_TO_UNCACHED(0x1fe104b0)
#define LS_GPIO_72_89_MULTI_CFG			PHYS_TO_UNCACHED(0x1fe104b4)
#define LS_GPIO_80_87_MULTI_CFG			PHYS_TO_UNCACHED(0x1fe104b8)
#define LS_GPIO_88_95_MULTI_CFG			PHYS_TO_UNCACHED(0x1fe104bc)
#define LS_GPIO_96_103_MULTI_CFG			PHYS_TO_UNCACHED(0x1fe104c0)
#define LS_GPIO_104_111_MULTI_CFG			PHYS_TO_UNCACHED(0x1fe104c4)
#define LS_GPIO_112_119_MULTI_CFG			PHYS_TO_UNCACHED(0x1fe104c8)
#define LS_GPIO_120_127_MULTI_CFG			PHYS_TO_UNCACHED(0x1fe104cc)
#define LS_GPIO_128_135_MULTI_CFG			PHYS_TO_UNCACHED(0x1fe104d0)
#define LS_GPIO_136_143_MULTI_CFG			PHYS_TO_UNCACHED(0x1fe104d4)
#define LS_GPIO_144_151_MULTI_CFG			PHYS_TO_UNCACHED(0x1fe104d8)
#define LS_GPIO_152_159_MULTI_CFG			PHYS_TO_UNCACHED(0x1fe104dc)

#define LS_GPIO_IRQ_EN_CFG				PHYS_TO_UNCACHED(0x1fe104e0)
#define LS_USB_PHY_CFG0					PHYS_TO_UNCACHED(0x1fe10500)
#define LS_USB_PHY_CFG1					PHYS_TO_UNCACHED(0x1fe10504)
#define LS_USB_PHY_CFG2					PHYS_TO_UNCACHED(0x1fe10508)
#define LS_USB_PHY_CFG3					PHYS_TO_UNCACHED(0x1fe1050c)
#define LS_PCIE0_CFG0					PHYS_TO_UNCACHED(0x1fe10530)
#define LS_PCIE0_CFG1					PHYS_TO_UNCACHED(0x1fe10534)
#define LS_PCIE0_CFG2					PHYS_TO_UNCACHED(0x1fe10538)
#define LS_PCIE0_CFG3					PHYS_TO_UNCACHED(0x1fe1053c)
#define LS_PCIE0_PHY_CFG0				PHYS_TO_UNCACHED(0x1fe10540)
#define LS_PCIE0_PHY_CFG1				PHYS_TO_UNCACHED(0x1fe10544)
#define LS_SATA0_REG0_CFG				PHYS_TO_UNCACHED(0x1fe10570)
#define LS_SATA0_REG1_CFG				PHYS_TO_UNCACHED(0x1fe10574)
#define LS_SATA1_REG0_CFG				PHYS_TO_UNCACHED(0x1fe10578)
#define LS_SATA1_REG1_CFG				PHYS_TO_UNCACHED(0x1fe1057c)
#define LS_SATA0_PHY0_CFG				PHYS_TO_UNCACHED(0x1fe10590)
#define LS_SATA0_PHY1_CFG				PHYS_TO_UNCACHED(0x1fe10594)
#define LS_SATA1_PHY0_CFG				PHYS_TO_UNCACHED(0x1fe10598)
#define LS_SATA1_PHY1_CFG				PHYS_TO_UNCACHED(0x1fe1059c)

#define LS_PIXCLK0_CTRL0_REG			PHYS_TO_UNCACHED(0x1fe10418)
#define LS_PIXCLK0_CTRL1_REG			PHYS_TO_UNCACHED(0x1fe1041c)
#define LS_PIXCLK1_CTRL0_REG			PHYS_TO_UNCACHED(0x1fe10420)
#define LS_PIXCLK1_CTRL1_REG			PHYS_TO_UNCACHED(0x1fe10424)

#define PIXCLK_CTRL0_PSTDIV_SET				(1 << 31)
#define PIXCLK_CTRL0_PSTDIV_PD				(1 << 30)
#define PIXCLK_CTRL0_PSTDIV_DF				(0X3f << 24)
#define PIXCLK_CTRL0_PLL_PD				    (1 << 7)
#define PIXCLK_CTRL0_PLL_LDF				(0xff << 16)
#define PIXCLK_CTRL0_PLL_ODF				(0x3 << 5)
#define PIXCLK_CTRL0_PLL_IDF				(0X7 << 2)
#define PIXCLK_CTRL0_REF_SEL				0X3

#define writel_reg_bit(addr, clear_bit, bit_val)	(*(volatile unsigned int*)(addr)) = (*(volatile unsigned int*)(addr)) & (~clear_bit) | bit_val

/* OTG regs */

/* USB regs */
#define LS_EHCI_BASE				PHYS_TO_UNCACHED(0x1f050000)
#define LS_XHCI_BASE 	                        PHYS_TO_UNCACHED(0x1f060000)

/* GMAC regs */

/* HDA regs */

/* SATAregs */
#define LS_SATA_BASE				PHYS_TO_UNCACHED(0x1f040000)

/* GPU regs */

/* DC regs */
#define	LS_DC_BASE					PHYS_TO_UNCACHED(0x1f010000)
#define LS_FB_CFG_DVO_REG				(0x1240)
#define LS_FB_CFG_VGA_REG				(0x1250)
#define LS_FB_ADDR0_DVO_REG				(0x1260)
#define LS_FB_ADDR0_VGA_REG				(0x1270)
#define LS_FB_STRI_DVO_REG				(0x1280)
#define LS_FB_STRI_VGA_REG				(0x1290)
#define LS_FB_ADDR1_DVO_REG				(0x1580)
#define LS_FB_ADDR1_VGA_REG				(0x1590)

#define LS_FB_CUR_CFG_REG				(0x1520)
#define LS_FB_CUR_ADDR_REG				(0x1530)
#define LS_FB_CUR_LOC_ADDR_REG			        (0x1540)
#define LS_FB_CUR_BACK_REG				(0x1550)
#define LS_FB_CUR_FORE_REG				(0x1560)

#define LS_FB_DAC_CTRL_REG				(0x1600)

/* SPI regs */
#define LS_SPI0_BASE				PHYS_TO_UNCACHED(0x1fd00000)
#define LS_SPI1_BASE				PHYS_TO_UNCACHED(0x1fd40000)
#define LS_SPI2_BASE				PHYS_TO_UNCACHED(0x1ff50000)
#define LS_SPI3_BASE				PHYS_TO_UNCACHED(0x1ff51000)
#define LS_SPI4_BASE				PHYS_TO_UNCACHED(0x1ff52000)
#define LS_SPI5_BASE				PHYS_TO_UNCACHED(0x1ff53000)

/* UART regs */
#define LS_UART0_REG_BASE				PHYS_TO_UNCACHED(0x1ff40000)
#define LS_UART1_REG_BASE				PHYS_TO_UNCACHED(0x1ff40400)
#define LS_UART2_REG_BASE				PHYS_TO_UNCACHED(0x1ff40800)
#define LS_UART3_REG_BASE				PHYS_TO_UNCACHED(0x1ff40c00)
#define LS_UART4_REG_BASE				PHYS_TO_UNCACHED(0x1ff41000)
#define LS_UART5_REG_BASE				PHYS_TO_UNCACHED(0x1ff41400)
#define LS_UART6_REG_BASE				PHYS_TO_UNCACHED(0x1ff41800)
#define LS_UART7_REG_BASE				PHYS_TO_UNCACHED(0x1ff41c00)
#define LS_UART8_REG_BASE				PHYS_TO_UNCACHED(0x1ff42000)
#define LS_UART9_REG_BASE				PHYS_TO_UNCACHED(0x1ff42400)

/* I2C regs */
//APB configured addr 0x1fe0,i2c0 addr is 0x1fe01000
#define LS_I2C0_REG_BASE				PHYS_TO_UNCACHED(0x1ff48000)
#define LS_I2C0_PRER_LO_REG			    (LS_I2C0_REG_BASE + 0x0)
#define LS_I2C0_PRER_HI_REG			    (LS_I2C0_REG_BASE + 0x1)
#define LS_I2C0_CTR_REG				    (LS_I2C0_REG_BASE + 0x2)
#define LS_I2C0_TXR_REG				    (LS_I2C0_REG_BASE + 0x3)
#define LS_I2C0_RXR_REG				    (LS_I2C0_REG_BASE + 0x3)
#define LS_I2C0_CR_REG				    (LS_I2C0_REG_BASE + 0x4)
#define LS_I2C0_SR_REG				    (LS_I2C0_REG_BASE + 0x4)

#define LS_I2C1_REG_BASE				PHYS_TO_UNCACHED(0x1ff48800)
#define LS_I2C1_PRER_LO_REG			    (LS_I2C1_REG_BASE + 0x0)
#define LS_I2C1_PRER_HI_REG			    (LS_I2C1_REG_BASE + 0x1)
#define LS_I2C1_CTR_REG				    (LS_I2C1_REG_BASE + 0x2)
#define LS_I2C1_TXR_REG				    (LS_I2C1_REG_BASE + 0x3)
#define LS_I2C1_RXR_REG				    (LS_I2C1_REG_BASE + 0x3)
#define LS_I2C1_CR_REG				    (LS_I2C1_REG_BASE + 0x4)
#define LS_I2C1_SR_REG				    (LS_I2C1_REG_BASE + 0x4)

#define LS_I2C4_REG_BASE				PHYS_TO_UNCACHED(0x1ff4a000)	//PIX0

#define CR_START					0x80
#define CR_STOP						0x40
#define CR_READ						0x20
#define CR_WRITE					0x10
#define CR_ACK						0x8
#define CR_IACK						0x1

#define SR_NOACK					0x80
#define SR_BUSY						0x40
#define SR_AL						0x20
#define SR_TIP						0x2
#define	SR_IF						0x1

/* PWM regs */
#define LS_PWM0_REG_BASE				PHYS_TO_UNCACHED(0x1ff5c000)
#define LS_PWM1_REG_BASE				PHYS_TO_UNCACHED(0x1ff5c010)

/* SDIO regs */
#define LS_SDIO0_BASE 				PHYS_TO_UNCACHED(0x1ff64000)
#define LS_SDIO1_BASE 				PHYS_TO_UNCACHED(0x1ff66000)

/* HPET regs */
#define LS_HPET0_BASE 				PHYS_TO_UNCACHED(0x1ff68000)
#define LS_HPET0_PERIOD				(LS_HPET0_BASE + 0x4)
#define LS_HPET0_CONF				(LS_HPET0_BASE + 0x10)
#define LS_HPET0_MAIN				(LS_HPET0_BASE + 0xF0)

#define LS_HPET1_BASE 				PHYS_TO_UNCACHED(0x1ff69000)
#define LS_HPET2_BASE 				PHYS_TO_UNCACHED(0x1ff6a000)
#define LS_HPET3_BASE 				PHYS_TO_UNCACHED(0x1ff6b000)

/* AC97 regs */
#define LS_AC97_REG_BASE			PHYS_TO_UNCACHED(0x1ff54000)

/* NAND regs */
#define LS_NAND_REG_BASE			PHYS_TO_UNCACHED(0x1ff58000)
#define LS_NAND_CMD_REG				(LS_NAND_REG_BASE + 0x0000)
#define LS_NAND_ADDR_C_REG			(LS_NAND_REG_BASE + 0x0004)
#define LS_NAND_ADDR_R_REG			(LS_NAND_REG_BASE + 0x0008)
#define LS_NAND_TIMING_REG			(LS_NAND_REG_BASE + 0x000c)
#define LS_NAND_IDL_REG				(LS_NAND_REG_BASE + 0x0010)
#define LS_NAND_STA_IDH_REG			(LS_NAND_REG_BASE + 0x0014)
#define LS_NAND_PARAM_REG			(LS_NAND_REG_BASE + 0x0018)
#define LS_NAND_OP_NUM_REG			(LS_NAND_REG_BASE + 0x001c)
#define LS_NAND_CSRDY_MAP_REG			(LS_NAND_REG_BASE + 0x0020)
#define LS_NAND_DMA_ACC_REG			(LS_NAND_REG_BASE + 0x0040)

/* ACPI regs */
#define LS_ACPI_REG_BASE			PHYS_TO_UNCACHED(0x1ff6c000)

/* DMA regs */
#define LS_DMA_ORDER0				PHYS_TO_UNCACHED(0x1fe10c00)
#define LS_DMA_ORDER1				PHYS_TO_UNCACHED(0x1fe10c10)
#define LS_DMA_ORDER2				PHYS_TO_UNCACHED(0x1fe10c20)
#define LS_DMA_ORDER3				PHYS_TO_UNCACHED(0x1fe10c30)


/* RTC regs */
#define LS_RTC_REG_BASE				PHYS_TO_UNCACHED(0x1ff6c100)
#define	LS_TOY_TRIM_REG				(LS_RTC_REG_BASE + 0x0020)
#define	LS_TOY_WRITE0_REG			(LS_RTC_REG_BASE + 0x0024)
#define	LS_TOY_WRITE1_REG			(LS_RTC_REG_BASE + 0x0028)
#define	LS_TOY_READ0_REG			(LS_RTC_REG_BASE + 0x002c)
#define	LS_TOY_READ1_REG			(LS_RTC_REG_BASE + 0x0030)
#define	LS_TOY_MATCH0_REG			(LS_RTC_REG_BASE + 0x0034)
#define	LS_TOY_MATCH1_REG			(LS_RTC_REG_BASE + 0x0038)
#define	LS_TOY_MATCH2_REG			(LS_RTC_REG_BASE + 0x003c)
#define	LS_RTC_CTRL_REG				(LS_RTC_REG_BASE + 0x0040)
#define	LS_RTC_TRIM_REG				(LS_RTC_REG_BASE + 0x0060)
#define	LS_RTC_WRITE0_REG			(LS_RTC_REG_BASE + 0x0064)
#define	LS_RTC_READ0_REG			(LS_RTC_REG_BASE + 0x0068)
#define	LS_RTC_MATCH0_REG			(LS_RTC_REG_BASE + 0x006c)
#define	LS_RTC_MATCH1_REG			(LS_RTC_REG_BASE + 0x0070)
#define	LS_RTC_MATCH2_REG			(LS_RTC_REG_BASE + 0x0074)

/* LPC regs */
#define LS_LPC_MEM_BASE	                        PHYS_TO_UNCACHED(0x1d000000)
#define LS_LPC_IO_BASE				PHYS_TO_UNCACHED(0x1f0d0000)
#define LS_LPC_REG_BASE				PHYS_TO_UNCACHED(0x1f0e0000)
#define LS_LPC_CFG0_REG				(LS_LPC_REG_BASE + 0x0)
#define LS_LPC_CFG1_REG				(LS_LPC_REG_BASE + 0x4)
#define LS_LPC_CFG2_REG				(LS_LPC_REG_BASE + 0x8)
#define LS_LPC_CFG3_REG				(LS_LPC_REG_BASE + 0xc)

/* For PS2 */
#define LS_PS2_DLL				PHYS_TO_UNCACHED(0x1ff4c008)
#define LS_PS2_DLH				PHYS_TO_UNCACHED(0x1ff4c009)

#define LS_SCACHE_LOCK_WIN0_BASE                PHYS_TO_UNCACHED(0x1fe10200)
#define LS_SCACHE_LOCK_WIN1_BASE                PHYS_TO_UNCACHED(0x1fe10208)
#define LS_SCACHE_LOCK_WIN2_BASE                PHYS_TO_UNCACHED(0x1fe10210)
#define LS_SCACHE_LOCK_WIN3_BASE                PHYS_TO_UNCACHED(0x1fe10218)
#define LS_SCACHE_LOCK_WIN0_MASK                PHYS_TO_UNCACHED(0x1fe10240)
#define LS_SCACHE_LOCK_WIN1_MASK                PHYS_TO_UNCACHED(0x1fe10248)
#define LS_SCACHE_LOCK_WIN2_MASK                PHYS_TO_UNCACHED(0x1fe10250)
#define LS_SCACHE_LOCK_WIN3_MASK                PHYS_TO_UNCACHED(0x1fe10258)

/* S3 Need */
/*
#define STR_XBAR_CONFIG_NODE_a0(OFFSET, BASE, MASK, MMAP) \
        daddi   v0, t0, OFFSET;     \
        dli     t1, BASE;           \
        or      t1, t1, a0;         \
        sd      t1, 0x00(v0);       \
        dli     t1, MASK;           \
        sd      t1, 0x40(v0);       \
        dli     t1, MMAP;           \
        sd      t1, 0x80(v0);
*/

#endif /* __MACH_LA_LS2K500_H */
